1. Field of the Invention
The invention relates in general to an output buffer of a semiconductor device, and more particularly to a high-voltage-sustainable output buffer of a semiconductor device.
2. Description of the Related Art
FIG. 1 shows a circuit diagram of an output buffer 100 in a SIO pad of a conventional flash memory. When the enable signal Z=1 (ZB=0), the output buffer 100 is in an active mode. The N-type metal-oxide-semiconductor (NMOS) transistor MN5 and the P-type metal-oxide-semiconductor (PMOS) transistor MP5 are both turned on, while the PMOS transistor MP3 and the NMOS transistor MN3 are both turned off. If the inputted data DATA=0, the PMOS transistor MP3A is turned on to output the voltage VDD to the node PU0 while the NMOS transistor MN3A is turned off. Since the transistor MN5 is turned on, the node PD0 has the same voltage VDD as the node PU0. As a result, the PMOS transistor MP0 is turned off by the gate voltage VDD while the NMOS transistor MN0 is turned on by the gate voltage VDD to output VSS (e.g. GND) as a data signal DQ (=DATA=0).
If the inputted data DATA=1, the transistor MP3A is turned off while the transistor MN3A is turned on to output the voltage VSS to the node PD0. Since the transistor MP5 is turned on, the node PU0 has the same voltage VSS as the node PD0. As a result, the transistor MN0 is turned off by the gate voltage VSS while the transistor MP0 is turned on by the gate voltage VSS to output VDD as the data signal DQ (=DATA=1).
When the enable signal Z=0 (ZB=1), the output buffer 100 is in a tri-state mode, the transistor MN5 and MP5 are both turned off such that the nodes PU0 and PD0 are both floating and the transistors MP0 and MN0 are both turned off. At the time, the data signal DQ is floating and the output buffer 100 is disabled. Owing that the transistor MP0 has fixed the bulk voltage to VDD as shown in FIG. 1, when an external high voltage (HV) larger than VDD is inputted to an output terminal of the transistor MP0, the voltage of the output terminal (i.e. the drain voltage of MP0) cannot be lifted up to HV due to turning on of the PN junction (drain P+ region to N-well) in the transistor MP0.
As such, the output buffer 100 of the conventional serial flash memory cannot work as a tri-state output buffer with an input high voltage larger than VDD. How to design a novel output buffer sustainable for high voltage input has become essential.